/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved.
 * Description: SML compute_roce table macro header file
 * Create: 2022/10/25
 */
#ifndef SML_TABLE_DEFINE_COMPUTE_ROCE_H
#define SML_TABLE_DEFINE_COMPUTE_ROCE_H

#include "node_id.h"

#define TBL_ID_GLOBAL_SM_NODE                  NODE_ID_SML0
#define TBL_ID_GLOBAL_SM_INST                  1

#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE       NODE_ID_SML0
#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST       2

#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE         NODE_ID_SML0
#define TBL_ID_NIC_RSS_CONTEXT_SM_INST         3

#define TBL_ID_NIC_ELB_SM_NODE                 NODE_ID_SML0
#define TBL_ID_NIC_ELB_SM_INST                 4

#define TBL_ID_NIC_FDIR_CFG_SM_NODE            NODE_ID_SML0
#define TBL_ID_NIC_FDIR_CFG_SM_INST            5

#define TBL_ID_BOND_FWD_SM_NODE                NODE_ID_SML0
#define TBL_ID_BOND_FWD_SM_INST                6

#define TBL_ID_ROCE_CCF_CTR_SM_NODE            NODE_ID_SML0
#define TBL_ID_ROCE_CCF_CTR_SM_INST            10

#define TBL_ID_ROCE_CCF_TOKEN_SM_NODE          NODE_ID_SML0
#define TBL_ID_ROCE_CCF_TOKEN_SM_INST          11

#define TBL_ID_ROCE_LOCK_BHEAP_SM_NODE         NODE_ID_SML0
#define TBL_ID_ROCE_LOCK_BHEAP_SM_INST         12

#define TBL_ID_CAR_SM_NODE                     NODE_ID_SML0
#define TBL_ID_CAR_SM_INST                     13

#define TBL_ID_CTR_DFX_PAIR_SM_NODE            NODE_ID_SML0
#define TBL_ID_CTR_DFX_PAIR_SM_INST            14

#define TBL_ID_BOND_LACPDU_SM_NODE             NODE_ID_SML0
#define TBL_ID_BOND_LACPDU_SM_INST             15

#define TBL_ID_PORT_CFG_SM_NODE                NODE_ID_SML1
#define TBL_ID_PORT_CFG_SM_INST                1

#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE       NODE_ID_SML1
#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST       2

#define TBL_ID_NIC_VLAN_FILTER_SM_NODE         NODE_ID_SML1
#define TBL_ID_NIC_VLAN_FILTER_SM_INST         3

#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE           NODE_ID_SML1
#define TBL_ID_NIC_FLEXQ_MAP_SM_INST           4

#define TBL_ID_NIC_VLAN_SM_NODE                NODE_ID_SML1
#define TBL_ID_NIC_VLAN_SM_INST                5

#define TBL_ID_NIC_MULTICAST_SM_NODE           NODE_ID_SML1
#define TBL_ID_NIC_MULTICAST_SM_INST           6

#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE    NODE_ID_SML1
#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST    7

#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE     NODE_ID_SML1
#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST     8

#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE    NODE_ID_SML1
#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST    9

#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE     NODE_ID_SML1
#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST     10

#define TBL_ID_ROCE_PF_PROBE_SM_NODE           NODE_ID_SML1
#define TBL_ID_ROCE_PF_PROBE_SM_INST           12

#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_NODE       NODE_ID_SML1
#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_INST       14

#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_NODE       NODE_ID_SML1
#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_INST       15

#define TBL_ID_ROCE_IPQCN_DIP_SM_NODE          NODE_ID_SML1
#define TBL_ID_ROCE_IPQCN_DIP_SM_INST          16

#define TBL_ID_CCF_IPQCN_SM_NODE               NODE_ID_SML1
#define TBL_ID_CCF_IPQCN_SM_INST               17

#define TBL_ID_DFX_LOG_POINTER_SM_NODE         NODE_ID_SML1
#define TBL_ID_DFX_LOG_POINTER_SM_INST         19

#define TBL_ID_CTR_DFX_S64_SM_NODE             NODE_ID_SML1
#define TBL_ID_CTR_DFX_S64_SM_INST             20

#define TBL_ID_CTR_DFX_S16_SM_NODE             NODE_ID_SML1
#define TBL_ID_CTR_DFX_S16_SM_INST             22

#define TBL_ID_FUNC_CFG_SM_NODE                NODE_ID_SML2
#define TBL_ID_FUNC_CFG_SM_INST                1

#define TBL_ID_NIC_RSS_INDIRECT2_SM_NODE       NODE_ID_SML2
#define TBL_ID_NIC_RSS_INDIRECT2_SM_INST       2

#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE      NODE_ID_SML2
#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST      3

#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_NODE     NODE_ID_SML2
#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_INST     5

#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_NODE       NODE_ID_SML2
#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_INST       6

#define TBL_ID_CTR_DFX_S32_SM_NODE             NODE_ID_SML2
#define TBL_ID_CTR_DFX_S32_SM_INST             4

#define TBL_ID_NIC_MAC_SM_NODE                 NODE_ID_SML3
#define TBL_ID_NIC_MAC_SM_INST                 1

#define TBL_ID_NIC_RSS_INDIRECT3_SM_NODE       NODE_ID_SML3
#define TBL_ID_NIC_RSS_INDIRECT3_SM_INST       2

#define TBL_ID_ROCE_PARAM_SM_NODE              NODE_ID_SML3
#define TBL_ID_ROCE_PARAM_SM_INST              3

#define TBL_ID_ROCE_IP_CTX_SM_NODE             NODE_ID_SML3
#define TBL_ID_ROCE_IP_CTX_SM_INST             4

#define TBL_ID_ROCE_IP_HASH_SM_NODE            NODE_ID_SML3
#define TBL_ID_ROCE_IP_HASH_SM_INST            5

#define TBL_ID_ROCE_QDFX_CTR_SM_NODE           NODE_ID_SML3
#define TBL_ID_ROCE_QDFX_CTR_SM_INST           6

#endif
